(a) Field of the Invention
The present invention relates to a layout method for a clock tree in a semiconductor device and, more particularly, to a technique for reduction of a clock skew in a clock signal distribution circuit.
(b) Description of the Related Art
Clock signal distribution circuit is generally used in a semiconductor integrated circuit for driving flip-flops or latches (hereinafter, referred to simply as flip-flops) in synchrony with one another. It is important to reduce the clock skew between clock signals supplied to the individual flip-flops for achieving a reliable operation of the semiconductor integrated circuit.
Patent Publication JP-A-3(1991)-232267 describes a clock signal distribution circuit formed as a mesh clock circuit having a mesh clock net for reducing the clock skew therein. In the proposed clock circuit, each clock branch connected to the input of a flip-flop is derived from the mesh clock net which is disposed over the entire chip area. The mesh clock net has a large line width for reduction of propagation delay of the clock signal.
In the proposed configuration, however, a clock skew remains in the mesh clock circuit because the line length from the clock receiver or root buffer to the respective flip-flops are not equal to one another. In addition, the mesh clock net generally includes unnecessary clock lines which have a large line width to thereby occupy a large chip area.
Patent Publication JP-A-5-54100 proposes a binary-tree clock signal distribution circuit, called clock-tree synthesis, wherein a computer-aided design (CAD) uses a specific technique to interpose relaying buffer drivers in the clock lines and to equalize the propagation delay from the clock receiver to the flip-flops for reduction of the clock skew. To equalize the propagation delay, the clock branches have detours to obtain a substantially equal length of the branches. In this publication, a tree configuration is first assumed in its entirety including a plurality of hierarchical clock nodes each having a plurality of branches extending therefrom.
The tree configuration is then determined in its exact location from a lower level to a higher level of the clock lines, so as to dispose the clock lines having a common node and a corresponding lower level node to have an equal length. The tree configuration is also determined in its location so that a plurality of buffer drivers disposed at the same level have an equal propagation delay by introducing detours in the clock lines.
In the proposed clock-tree synthesis, it is generally difficult or substantially impossible to equalize the loads for the buffer drivers, and accordingly, a significant clock skew still remains in the clock signal distribution circuit.